1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to activation of a sense amplifier thereof. The present invention has particular applicability for a dynamic random access memory device.
2. Description of the Background Art
FIG. 5 is a block diagram showing one example of a well-known conventional dynamic random access memory (hereinafter referred to as a DRAM). Referring to FIG. 5, the DRAM comprises a memory array 58 comprising memory cells for storing a data signal, an address buffer 54 receiving an address signal to select a memory cell, a row decoder 55 and a column decoder 56 which decode an address signal, and a sense amplifier 63 connected to the memory array 58 and amplifying and reading a signal stored in the memory cell. An input buffer 59 for inputting the data signal and an output buffer for outputting the data signal are connected to the memory array 58 through an I/O gate 57.
The address buffer 54 is connected to receive external address signals ext. A0 to A9 or internal address signals Q0 to Q8 generated from a refresh controller 52. The refresh controller 52 drives a refresh counter 53 in response to the timing of RASand CASsignals applied to a clock generator 51.
FIG. 6A is a circuit diagram showing a peripheral circuit of the memory array 58 of the DRAM shown in FIG. 5. FIG. 6B is a timing chart for describing its operation thereof. These are seen, for example, on pages 252 to 253 in a Digest of Technical Papers of International Solid State Circuit Conference held on Feb. 15, 1985 (Session XVII).
Referring to FIG. 6A, a memory cell M is connected to a bit line BLj and a word line WLi. The memory cell M comprises a capacitor Cs for storing a data signal and an NMOS transistor Qs for switching. A sense amplifier 63 comprises a CMOS flip-flop connected between the bit lines BLj and BLj. This CMOS flip flop comprises a P channel sense amplifier comprising PMOS transistors Q3 and Q4, and an N channel sense amplifier comprising NMOS transistors Q1 and Q2. The CMOS flip-flop is connected to the power supply Vcc and the ground Vss through a PMOS transistor Q11 and an NMOS transistor Q12. The transistors Q11 and Q12 have their gates connected to receive sense trigger signals Soand So, respectively. An equalize circuit 61 comprises an NMOS transistor Q5 connected between the bit lines BLj and BLjand NMO transistors Q6 and Q7 connected in series. The gates of these transistors are connected to receive an equalize signal EQ.
A bit line precharge voltage (hereinafter referred to as a V.sub.BL) generation circuit 62 is connected to the junction of the transistors Q6 and Q7 through an NMOS transistor Q10. An I/O gate 57 comprises an NMOS transistor Q8 connected between the bit line BLj and an I/O line and an NMOS transistor Q9 connected between the bit line BLjand an I/ line. The transistors Q8 and Q9 have their gates connected to receive a signal Yj from a column decoder. The signal generation circuit 69 is provided for generating control signals PR, EQ, So and Sofor controlling these circuits.
Referring to FIGS. 6A and 6B, a description is made of reading operation and refresh operation of the DRAM.
First, the equalize signal EQ and the precharge signal PR are generated from the signal generation circuit 69. The transistors Q10, Q5, Q6 and Q7 turn on in response to these signals and the bit line pair of BLj and BLjare equalized to be brought to VBL (in general a voltage Vcc/2). After a RASsignal falls, the signals EQ and PR change to a low level. Then, a word line signal WLi changes to a high level and the switching transistor Qs of the memory cell M turns on. A voltage of the bit line BLj changes a little when a signal from the memory cell M is applied, whereby a small voltage difference between the bit line BLjand the bit line BLj is generated.
On the other hand, at this time, the signals So and Sochange and the sense amplifier is driven. Then, the small voltage difference generated between the bit lines is amplified by the sense amplifier 63. Thereafter, by applying a high level signal Yj, the amplified data signal is applied to the I/O line pair through the transistors Q8 and Q9.
In refresh operation, the amplified data signal is not applied to the I/O line pair, but it is only applied to the capacitor Cs of the memory cell again.
FIG. 7 is a conceptual diagram showing the corresponding relation between regions of the memory array 58 and the sense amplifier 63 shown in FIG. 5 and the address signal. As shown in FIG. 7, the regions comprising the memory array 58 and the sense amplifier 63 correspond to row address signals RA.sub.8 and column address signals CA.sub.8 and can be divided into four regions I to IV. Therefore, for example, the address signal for designating a certain memory cell in the region IV comprises the row address signal RA.sub.8 of "1" and the column address signal CA.sub.8 of "1".
FIG. 8 is a circuit diagram showing partially the regions III and IV shown in FIG. 7. In the region III, there are provided memory cells MA1 to MAn and sense amplifiers SA1 to SAn which are connected to a bit line pair of BL and BL. Similarly, in the region IV, there are provided memory cells MB1 to MBn and sense amplifiers SB1 to SBn. An activation line SN is connected to the ground Vss through the transistor Q12 and the activation line SP is connected to the power supply Vcc through the transistor Q11. Each of the memory cells and the sense amplifiers has the same circuit structure as that shown in FIG. 6A.
An example of prior art of particular interest to the present invention is seen in Japanese Patent Laying-Open Gazette No. 68797/1986. In this prior art, ability to drive sense amplifier is varied in response to a column address signal.
Another example of the prior art of particular interest to the present invention is seen in Japanese Patent Laying-Open Gazette No. 20297/1986. This prior art discloses an example of a circuit which drives a plurality of sense amplifiers with signals having different timings. These sense amplifiers are driven without responding to the address signal.
A further example of the prior art of particular interest to the present invention is seen in IEEE Journal of Solid State Circuit (VOL. SC-22, No. 5) issued in October 1987 (pages 651-656). In this example, ability to drive a sense amplifier is raised in response to driving signals having different timings.
Still another example of the prior art of particular interest to the present invention is seen in Japanese Patent Laying-Open Gazette No. 223994/1984. In this example, there is shown a timing control of the equalization of a bit line pair.
FIG. 9 is a timing chart showing changes of each signal when the sense amplifier shown in FIG. 8 is activated. Referring to FIGS. 8 and 9, for example when the data signal of the memory cell MB1 in the region IV is read in reading operation, all sense amplifiers SA1 to SAn and SB1 to SBn in the regions III and IV are activated. More specifically, as described above, the transistors Q12 and Q11 turn on in response to the sense trigger signals So and So. A small voltage generated on the bit line pair of BL and BLin the regions III and IV is amplified by the activation of these sense amplifiers. Since all sense amplifiers in the regions III and IV are activated at the same time, a current Is consumed by the sense amplifiers is increased rapidly and shows a peak value Ia. The rapid increase in this consumption of the current Is causes the supply voltage to drop and this drop of the supply voltage causes the sensitivity of the sense amplifier to deteriorate.